This invention relates to a semiconductor device having a lightly-doped-drain structure and a method of manufacturing the same.
Generally, a fine structure MOS semiconductor device has a lightly-doped-drain (LDD) structure to suppress generation of hot carriers. A method of manufacturing a prior art MOS transistor having an LDD structure will be described with reference to FIG. 1.
First, gate oxide film 2 is formed on p-type silicon substrate 1, for instance. Then, a polycrystalline silicon film is formed on the entire surface and selectively etched to form gate electrode 3 on gate oxide film 2. Then, with gate electrode 3 as a mask, phosphorus is ion-implanted into substrate 1, thus forming n.sup.- -type impurity regions 4A and 4B in the surface area of substrate 1. Subsequently, a CVD oxide film is formed over the entire surface and selectively etched by a reactive ion-etching (RIE) process to leave spacers 5A and 5B which are in contact with the side wall of gate electrode 3. Subsequently, with gate electrode 3 and spacers 5A and 5B as a mask, arsenic is ion-implanted into substrate 1, thus forming n.sup.+ -type regions 6A and 6B in n.sup.+ -type regions 4A and 4B.
N.sup.- - and n.sup.+ -type regions 4A and 6A constitute source region 7, and n.sup.- - and n.sup.+ -type regions 4B and 6B constitute drain region 8.
Thereafter, as is well known in the art, an insulating layer is formed on the semiconductor structure shown in FIG. 1, contact holes are formed in the insulating layer, then aluminum is deposited, for instance, on the insulating layer and patterned to form an aluminum wiring layer.
In the MOS transistor of the LDD structure obtained in this way, the electric field in a channel region near drain region 8 is alleviated, so that generation of hot carriers in drain region 8 is suppressed to obtain a highly reliable operation.
In the MOS transistor of the structure of this type, the length of the diffusion region extending from the end of n.sup.+ -type region 6B of the n.sup.- -type region 4B constituting the drain region 8 is made as large as possible, while holding the parasitic resistance of the diffusion portion to be less than a permissible value to enhance the breakdown voltage. For example, with the MOS transistor having an LDD structure formed on the basis of a 0.8 to 1.2 .mu. rule, spacer 5B for determining the length of the diffusion portion noted above is set to 0.20 to 0.25 .mu.m.
Further, in the fine structure MOS transistor n.sup.+ -type regions 6A and 6B, constituting source and drain regions 7 and 8, have a depth of approximately 0.2 .mu.m. This is done so that in order to alleviate the electric field in the channel region near drain region 8 in a case where n.sup.+ -type regions 6A and 6B are deeper, it is necessary to form n.sup.- -type regions 4A and 4B to be deep. When n.sup.- -type regions 4A and 4B are formed to be deep, a short-channel effect is liable to result. Where the width of n.sup.+ -type regions 6A and 6B is set to 0.20 to 0.25 .mu.m and the depth of n.sup.+ -type regions 6A and 6B is set to approximately 0.2 .mu.m, the end of n.sup.+ -type regions 6A and 6B is found on the lower side of spacers 5A and 5B.
In FIG. 2, the rate of triode channel current reduction, with respect to the stress application time in a MOS transistor of an LDD structure shown in FIG. 1, and a MOS transistor with an ordinary structure without an impurity region, is shown as respective solid lines A and B. The MOS transistor having an ordinary structure used for a bias stress test has a gate length of 0.9 .mu.m and a film thickness of 200 .ANG. (0.02 .mu.m). The impurity concentration of the n.sup.- -type region is 1.times.10.sup.18 cm.sup.-3. The other conditions are the same as the MOS transistor having an ordinary structure.
In FIG. 2, the ordinate is taken for the percentage of the difference .DELTA.ID between the drain current ID, obtained when a gate voltage of 2 V and a drain voltage of 6.5 V are applied, and the drain current obtained when bias stress (including a gate voltage of 3 V and a drain voltage of 8 V) is applied with respect to the current ID; the abscissa is taken for the bias stress application period.
As is obvious from solid line A in FIG. 2, with the MOS transistor having an ordinary structure, the drain current reduction rate is increased at a comparatively greater rate with increasing stress application time. As is obvious from solid line B, in the LDD structure MOS transistor the reduction rate of drain current varying with change in the stress application time is comparatively low, but the drain current reduction rate in an initial stage of the bias stress test, i.e., initial degradation, is large. In the LDD structure MOS transistor, the initially expected high reliability can not be attained.